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Si4455
6. Data Handling and Packet Handler
6.1. RX and TX FIFOs
Two 64-byte FIFOs are integrated into the chip, one for RX and one for TX. Writing to command register 66h loads
data into the TX FIFO and reading from command register 77h reads data from the RX FIFO. For packet lengths
greater than 64 bytes, RX_FIFO_ALMOST_FULL and TX_FIFO_ALMOST_EMPTY status bits and interrupts can
be used to manage the FIFO. The threshold value for these can be configured via the WDS radio configuration
application GUI. The maximum payload length supported in packet handler mode is 255 bytes.
6.2. Packet Handler
The Si4455 includes integrated packet handler features such as preamble and sync word detection as well as CRC
calculation. This allows the chip to qualify and synchronize with legitimate transmissions independent of the
microcontroller. These features can be enabled using the RCA. In this setup, the preamble and sync word length
can be modified and the sync word pattern can be selected. If the preamble is greater than or equal to 4 bytes, the
device uses the preamble detection circuit with a 2-byte detection threshold. If the preamble is less than 32 bits,
then at least two bytes of sync word are required plus at least one byte of 0101 pattern (3 bytes total). In this case,
preamble detection is skipped, and only sync word detection is used. For any combination of preamble and sync
word less than three bytes, the device will use direct mode. The general packet structure is shown in Figure 16.
The EZConfig setup also provides the option to select a variable packet length. With this setting, the receiver is not
required to know the packet length ahead of time. The transmitter sends the length of the packet immediately after
the sync word. The packet structure for variable length packets is shown in Figure 17.
Preamble
0 – 255 Bytes
Sync Word
1 – 4 Bytes
Data
1 – 255 Bytes
CRC
2 Bytes
Figure 16. Packet Structure for Fixed Packet Length
Preamble
0 – 255 Bytes
Sync Word
1 – 4 Bytes
Length
1 Byte
Data
1 – 255 Bytes
CRC
2 Bytes
Figure 17. Packet Structure for Variable Packet Length
6.3. Direct Mode
In direct mode, the packet handler (including FIFO) is bypassed, and the host MCU must feed the data stream to
the device in TX mode and read out the data stream in RX mode via GPIOs. The host MCU will process the data
and perform packet handler functions. This is commonly used to support legacy implementations where host MCU
software exists or to support non-standard packet structures. Some examples are packets with non 1010 preamble
pattern, no preamble or sync word, or sync word with no edge transitions. WDS provides example projects to
support both packet handler and direct modes.
Rev 1.1
31
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